FIGS. 7(a) and 7(b) show a prior art production method of a self-aligned gate FET recited in Electronics Information and Communication Engineer's Society of Japan, Electronic Device Research Institute report, ED86-9, pp. 23 to 28, "Optimization of MMIC GaAs Advanced SAINT Structure" (reference No. 1).
In FIGS. 7(a) and 7(b), reference numeral 1 designates a GaAs substrate. A p well 24 is produced in the substrate 1. N-channel region 3 is produced in the p well 24. N.sup.+ ion implanted regions 16 and 17 constitute a source and a drain region, respectively. Numeral 12 designates a through-film for implantation comprising SiN which functions as a mask for ion implantation. Numeral 23 designates a dummy gate comprising a T-shaped photoresist. Numeral 25 designates a SiO.sub.2 film. Numeral 26 designates a gate electrode. Numerals 61 and 71 designate a source and a drain electrode, respectively.
It is described in the reference No. 1 that an n.sup.+ ion implantation is carried out using the T-shaped photoresist as a mask (FIG. 7(a)), and further a pattern inversion is carried out and the gate electrode is produced by the lift-off method, resulting in a structure shown in FIG. 7(b).
However, in the FET produced in this way, because the source and drain regions are symmetrical with respect to the gate electrode 26, the interval between the source region 16 and the drain region 17 is reduced as is the gate length. The substrate leakage current between source and drain increases, thereby causing the short channel effect. In addition, when the distance between the gate and source is shortened to reduce the source resistance, the distance between the gate and drain is also necessarily shortened and the gate drain breakdown voltage is reduced.
In order to reduce the short channel effect and increase the gate drain breakdown voltage, a conventional methods of producing an FET having an asymmetrical gate, described in the following, is proposed.
One of them, which is also recited in the reference No. 1, will be described with reference to FIGS. 8(a) and 8(b). In FIGS. 8(a) and 8(b), the same reference numerals designate the same parts as in FIGS. 7(a) and 7(b). It is described in the reference No. 1 that the device is produced as follows:
After p well 24 and n type layer 3 are produced by ion implantation, a plasma CVD SiN film 12 is deposited, and a T-shaped dummy gate 23 is produced thereon. Using this dummy gate 23 as a mask, n.sup.+ ion implantation is carried out (FIG. 8(a)). The angle of ion implantation is determined such that the distance between the gate electrode and the end of the n.sup.+ layer at the drain side (Lgd) is larger than the distance between the gate electrode and the source side (Lsg). Next, using an inverted pattern of dummy gate 23 as a mask, a Schottky junction part is opened and Mo/Au is deposited by DC sputtering. Then, by flattening the Au using diagonal direction ion milling, a gate electrode 26 is produced only on the Schottky junction part and finally ohmic electrodes 61, 71 are produced by lift-off and sintered, thereby resulting in a device of FIG. 8(b).
The n.sup.+ implanted layers which are produced by the diagonal direction ion implantation using the T-shaped gate electrode which is symmetric with respect to the source and drain as a mask results in a difference between the gate-source distance Lsg and the gate-drain distance Lgd. This makes it possible to reduce the source resistance and to enhance the gate drain breakdown voltage at the same time. Furthermore, this enables a long distance between the source and the drain region, resulting in reduction in the short channel effect.
FIGS. 9(a)-9(h) show another prior art method of producing FET having an asymmetric self-aligned gate, which is recited in IEEE Transactions on Electron Devices, Vol. 35, No. 5, May 1988, pp. 615 to 622, "A New Refractory Self-Aligned Gate Technology for GaAs Microwave Power FET's and MMIC's" (reference No.2).
The production method will be described.
As shown in FIG. 9(a), a SiON film 12 is produced as through-film for implantation on a GaAs substrate 1, and thereafter, an active channel region 3 of FET is produced by selective ion implantation of silicon ions. Thereafter, the SiON film 12 is removed, a TiWN film is produced on the entire surface by sputtering, an etching mask comprising Ni 14 is produced at a gate electrode production region and the TiWN layer is processed so as to have a gate configuration 13 by reactive ion etching (FIG. 9(b)).
Next, a photoresist pattern 15 of a configuration that covers the drain side of the gate electrode 13 is produced as a mask for n.sup.+ ion implantation, and n.sup.+ ion implantation is carried out using the same as a mask to produce asymmetrical n.sup.+ ion implanted regions 16 and 17 among which the drain region is located further from the gate electrode 13 than the source region (FIG. 9(c)).
Next, the photoresist 15 and Ni film 14 are removed, a SiON film 18 is provided on the entire surface of the substrate as a protection film which functions as an anneal cap and then an annealing is carried out to activate the implanted ions in the regions 16 and 17 (FIG. 9(d)). Thereafter, a flattening photoresist 19 is provided on the entire surface of substrate (FIG. 9(e)), gate 13 is exposed by etching back, and ohmic metals 20 and 21 which are to be a source electrode and a drain electrode are produced by burying metal FIG. 9(f)).
Next, a low resistance metal 22 of Ti/Au is produced on the gate electrode 13 by evaporation and lift-off (FIG. 9(g)), and thereafter a SiN film 27 is produced on the surface and Au electrodes 28 are produced on the ohmic electrodes 20 and 21 via TiWN layers 29. Further, an opening is provided at a part of the source electrode 20 from the rear surface of the substrate 1 and Au electrode 28 is plated on the rear surface covering the side wall of the opening and the entire rear surface of substrate, thereby completing the device (FIG. 9(h)).
In this production method, the photoresist pattern 15 is produced only covering the drain side of the gate electrode 13, so that n.sup.+ layer producing ions are not implanted into the vicinity of the gate electrode at the drain side. Thus an asymmetrical gate FET is produced.
In the prior art production method shown in FIGS. 8(a) and 8(b) the asymmetry of the production position of n.sup.+ layer with respect to the gate is realized by a diagonal implantation, and the angle of the diagonal implantation varies depending on position in the GaAs wafer surface. The position of the end portion of n.sup.+ layer is likely to vary depending on the configuration of T-shaped gate which functions as an implantation mask. That is, the position where the n.sup.+ layer is produced is likely to be affected by variations in the configuration of T-shaped gate cause variations in characteristics.
In the prior art production method shown in FIGS. 9(a)-9(h), the photoresist mask which is produced at the drain side of the gate is position determined only by photolithography and therefore the positioning of the photoresist mask is quite unstable. That is, the precision of the photoresist mask largely depends on the performance of the photolithography apparatus and it may possibly vary from run to run. Therefore, an asymmetrical gate FET having a stable gate drain distance and a gate source distance as designed can not be produced with high reproducibility.